1. Field of the Invention
The present invention relates to a memory of a clock-synchronized type for inputting and outputting data. In particular, the present invention relates to a synchronous memory which includes a register for setting an operation mode and operates in an operation mode (defined by burst length, wrap type, and CAS latency) which is determined in accordance with the contents set in the mode register.
2. Description of the Related Art
In recent years, memories which permit faster access have been in demand due to improvements in the operation frequencies of microprocessors. Answers to such demands include clock-synchronized type memories, e.g., synchronous DRAMs.
A synchronous DRAM includes a mode register for setting an operation mode. By setting an operation mode (defined by burst length, wrap type, and CAS latency) in the mode register, the synchronous DRAM can perform an operation which is optimally selected for any given system incorporating the synchronous DRAM.
Herein, the "burst length" refers to the number of data units which can be consecutively input or output. For example, either 1, 2, 4, 8 or a full-page can be selected as the burst length. The "wrap type" refers to the manner in which column addresses, which are internally generated during a burst access, are varied. For example, either a sequential method (under which the column addresses are sequentially changed within the same bank) or an interleave method (under which the column addresses are scrambled) can be selected as the wrap type. The "CAS latency" refers to the number of clock pulses that elapse before the first data is read after inputting a read command. For example, either 1, 2, or 3 can be selected as the CAS latency.
FIG. 18 is a block diagram schematically illustrating the structure of a synchronous DRAM.
The synchronous DRAM shown in FIG. 18 includes a memory cell array 21, a row decoder 22, a column decoder 23, a row address buffer 24, a column address buffer 25, a data control circuit 26, a data input/output buffer 27, a control logic 28, and a mode register setting circuit 29. The mode register setting circuit 29 includes a mode register 31 as shown in FIG. 19.
In FIG. 18, SS denotes an output signal from the mode register within the mode register setting circuit 29, which is input to the control logic 28.
As can be seen in FIG. 19, the mode setting function of the synchronous DRAM is accomplished by inputting to the input-only pins various codes (commands) which represent operations. Usually, a chip select signal CS/, a row address strobe signal RAS/, a column address strobe signal CAS/, and a write enable signal WE/ are set to the "Low" level, and address terminals A0 to A6 are utilized as terminals for inputting data.
FIG. 19 is a simplified diagram showing the structure of the mode register setting circuit 29. The mode register setting circuit 29 includes AND gates 35, 36, and 37 as well as the mode register 31. The mode register 31 includes 3-bit D flip-flops 32, 33, and 34. The outputs of the D flip-flops 32, 33, and 34 represent the burst length, wrap type, and CAS latency, respectively. In practice, however, one flip-flop may be dedicated for each of 1, 2, 4, 8, and a full-length that defines the burst length; one flip-flop is similarly dedicated to each value of any other parameter, although not shown in FIG. 19.
Each of the AND gates 35, 36, and 37 is opened responsive to a mode register set signal MRS. The output of each of the AND gates 35, 36, and 37 is determined in accordance with the value of a 7 bit address A0 to A6 and the mode register set signal MRS. The mode register set signal MRS is the output of the AND gate 38. It is possible to set a given operation mode in the mode register 31 by setting the chip select signal CS/, the row address strobe signal RAS/, the column address strobe signal CAS/, and the write enable signal WE/ to the "Low" level and concurrently supplying a predetermined address value A0 to A6.
A mode setting in the mode register is performed in an initialization routine before memory access. Before access to a memory occurs, the user sets the content of the mode register in accordance with the memory accessing specification and intended mode of use of the memory. Among the parameters of the operation mode which is set in the mode register, the "CAS latency" refers to the number of clock pulses that elapse before the first data is read or written after latching a CAS address (column address) during a memory access. Therefore, if the CAS latency is set to "2", the first data will be read or stored 2 clock pulses after latching a CAS address.
In general, a semiconductor memory such as a DRAM requires some time after power is supplied to the memory until the power voltage Vcc becomes stabilized to a predetermined potential so as to stabilize the internal circuitry. A given operation mode may be set in the mode register in the above-described sequence. This prolongs the time which elapses before the memory becomes accessible after power is supplied. Furthermore, it is necessary to set a mode via an initialization routine or the like, which needs to be run before a memory access occurs after supplying power.
As a solution to the above problem, it has been proposed in the field of synchronous DRAMs to set initial values for the mode register by means of non-volatile switching elements (e.g., laser fuses or electric fuses) and automatically set the initial values in the mode register upon detecting the rise of the power voltage after power is supplied, thereby reducing the complexity associated with mode setting via an initialization routine or the like (Japanese Laid-Open Publication No. 7-93970).
In general, a higher power potential makes for a shorter memory access time, thereby making it possible to reduce the latency, assuming that the memory operates with the same clock signal. In this case, prefixing the content of the mode register will make it impossible to set a latency which is optimum in view of the power potential.
Moreover, it would complicate the process and management of manufacture to produce multiple types of devices with different operation modes which are in accordance with respectively different device specifications.